1. Field of the Invention
The present invention relates to a memory device that shares circuit construction for repairing fail, and more particularly to a memory device that makes respective memory banks share a fail-repairing circuit installed outside the memory banks instead of installing separate fail-repairing circuits in the memory banks, respectively.
2. Description of the Prior Art
With the high integration of a semiconductor memory device, the number of memory cells packaged on a chip becomes greatly increased. However, in spite of the development of fabrication technology of a high-integration memory device, there is always a probability of fail occurrence in memory cells or word/bit lines. Such a probability becomes higher as the integration of a memory device becomes higher.
Meanwhile, the memory device is also required to operate at a high frequency. As the speed of the memory device becomes high, a bank structure has been proposed. For example; 2, 4, 8 or 16 banks are provided inside the memory device. In particular, the bank structure is generally used in a synchronous type DRAM such as a DDR SDRAM.
In relation to the fail of a memory device, a memory device adopting a bank structure is provided with repair-related circuits installed in the respective banks. These repair-related circuits in the respective banks repair the fail if the fail occurs in the corresponding banks.
FIG. 1 shows the construction of banks of a conventional memory device that include repair circuits. In FIG. 1, the conventional memory device is composed of four banks, and signals and functions of constituent elements of the construction of FIG. 1 will briefly be explained.
The term “address” represents a row address or a column address commonly applied to all memory banks.
The term “bank address” represents an address for selecting a specified bank among a plurality of banks 101 to 104.
The term “command” represents a signal for setting an inner operation of the memory device such as active, pre-charge, read, write, etc.
The term “bank control unit” represents a circuit for instructing a specified bank designated by the bank address to perform an operation set by the command. For example, if a bank 102 is selected by the bank address and a write command is applied to the bank control unit 10, the bank control unit 10 controls a write operation of the bank 102.
The terms “A0, A1, A2 and A3” serve to input/release an effective address to/from a bank selected by the bank control unit 10.
The bank 101 includes an address latch 11, a pre-decoder 12, a fuse and control unit 13, a decoder and block control unit 14 and a memory cell array 15.
The address latch 11 holds the address for a predetermined time.
The pre-decoder 12 pre-decodes the address B0 outputted from the address latch 11.
The address C0 outputted from the pre-decoder is applied to the fuse and control unit 13 and the decoder and block control unit 14.
The fuse and control unit 13 cures the fail occurring in a specified memory cell. The fuse and control unit 13 determines whether to repair the input address by comparing repair information stored in a fuse with the address, and outputs a redundancy operation signal D0 for the repair.
If the input address is a normal address as a result of comparison, the decoder and block control unit 14 receives the address C0 and accesses the corresponding specified cell of the memory cell array 15. In this case, the specified cell represents a normal cell. However, if the input address is a fail address, the decoder and block control unit 14 receives the address D0 and accesses the corresponding specified cell of the memory cell array 15. In this case, the specified cell represents a redundancy cell.
The structures of the banks 102, 103 and 104 are the same as that of the bank 101.
FIG. 2 shows the construction of banks of another conventional memory device that include repair circuits.
The construction of FIG. 2 is different from that of FIG. 1 such that the address B0 outputted from the address latch is directly applied to the fuse and control unit. Specifically, the fuse and control unit 13 of FIG. 1 receives the output of the pre-decoder 12, but the fuse and control unit of FIG. 2 directly receives the output of the address latch.
The remaining construction of FIG. 2 is the same as that of FIG. 1.
As shown in FIGS. 1 and 2, in the conventional memory device, the respective banks have the corresponding fuse and control units provided inside the banks, and thus the repairing circuits of the conventional memory device have the disadvantages in size and efficiency.
Specifically, in spite of the great development of fabrication technology, the fail cells are not produced at constant rates with respect to the respective banks. For example, in some banks, many fail cells may be produced, while in other banks, a few or almost no fail cell may be produced. Since the rates of fail cell production are different by banks, it is inefficient to provide the constant number of fuse and control units by banks. Also, in the case of the specified banks in which a few fail cells are produced, the fuse and control units unnecessarily occupy a large space.